Design and Implementation of Reconfigurable Stream Processor in Multimedia Applications

被引：0
作者：
Xiao, Yu [1 ]
Liu, Leibo [1 ]
Wei, ShaoJun [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Tsinghua Natl Lab Informat Sci & Technol, Beijing 100084, Peoples R China
来源：
2008 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1 AND 2: VOL 1: COMMUNICATION THEORY AND SYSTEM | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposed a Reconfigurable Stream Processor applied in multimedia applications. Based on the unique parallel stream processing framework and optimized algorithm mapping method, the reconfigurable processor exploits the parallelism of complex algorithms and provides a high flexibility during run-time to adapt to various applications. The architecture of processor is implemented and verified on the development board of ARM926EJS plus Xilinx Virtex-4XC4VLX80. A H.264 video codec is implemented to verify the reconfigurable architecture, achieving 58%similar to 130% speed boost compared with traditional reconfigurable architectures such as MorphoSys and PACT.
引用
收藏
页码：1510 / 1514
页数：5
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