FPGA Implementation of Blind Adaptive Decision Feedback Equalizer

This paper considers field programmable gate array (FPGA) implementations for blind adaptive decision feedback equalizer (DFE) based on the IP core reported in [1]. The design can achieve channel equalization for 16-QAM and 64-QAM. Constant modulus algorithm (CMA) and multi-modulus algorithm (MMA) are considered for update the coefficients in the blind mode of operation which are followed by decision-directed (DD) mode. The system can work at a maximum clock frequency of 22 MHz. The design steps first consider fixed-point simulations using MATLAB fixed-point toolbox follows by FPGA implementations. The implementations are divided into complex weight update module, output computation module, error adjustment module, and decision device module. Finally, the DFE is implemented using Xilinx Virtex-II XC2VP100 FPGA.