A System-Level Optimization Framework for High-Performance Networking

被引:0
作者
Benson, Thomas M. [1 ]
机构
[1] Georgia Tech Res Inst, Sensors & Electromagnet Applicat Lab, Atlanta, GA 30332 USA
来源
2014 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC) | 2014年
关键词
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Processing data in a streaming fashion is involved in many applications, including radar, electro-optical and infrared imaging, and other scenarios in which real-time data is acquired from sensors. While the difficulty of processing such data in real-time or in an otherwise timely fashion is the topic of much research, transferring the data between machines or devices is also a key challenge. This work investigates the utilization of commodity high-speed networking products - in particular, 40 gigabit Ethernet - for supporting high-speed data transfer in streaming applications. For such systems, optimizing the system configuration to support data transfers approaching line rate is critical. This work demonstrates the use of an optimization framework to explore the impact of various system-level optimization settings, including kernel module settings, network interface driver-level settings, kernel buffer sizes, thread and CPU core scheduling, non-uniform memory access (NUMA) scheduling, interrupt handling, and CPU power-saving state management.
引用
收藏
页数:6
相关论文
共 50 条
[41]   System-Level Performance of Interference Alignment [J].
Mungara, Ratheesh K. ;
Morales-Jimenez, David ;
Lozano, Angel .
IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, 2015, 14 (02) :1060-1070
[42]   System-level Performance of Interference Alignment [J].
Mungara, Ratheesh K. ;
Morales-Jimenez, David ;
Lozano, Angel .
2014 IEEE GLOBAL COMMUNICATIONS CONFERENCE (GLOBECOM 2014), 2014, :1673-1678
[43]   CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors [J].
Asadi, Hossein ;
Haghdoost, Alireza ;
Ramezani, Morteza ;
Elyasi, Nima ;
Baniasadi, Amirali .
MICROELECTRONICS RELIABILITY, 2014, 54 (05) :1009-1021
[44]   OTA Performance Space Modeling for System-Level Optimization of SC-circuits [J].
Schreiber, David ;
Kampe, Juergen .
2020 27TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2020,
[45]   System-Level Design Optimization of a Hybrid Tug [J].
Hofman, T. ;
Naaborg, M. ;
Sciberras, E. .
2017 IEEE VEHICLE POWER AND PROPULSION CONFERENCE (VPPC), 2017,
[46]   Design optimization with system-level reliability constraints [J].
McDonald, M. ;
Mahadevan, S. .
JOURNAL OF MECHANICAL DESIGN, 2008, 130 (02)
[47]   System-Level Optimization of Passive Energy Balancing [J].
Shaw, Alexander D. ;
Zhang, Jiaying ;
Wang, Chen ;
Woods, Benjamin K. S. ;
Friswell, Michael I. .
AIAA JOURNAL, 2022, 60 (09) :5570-5580
[48]   System-level power optimization: Techniques and tools [J].
Benini, Luca ;
De Micheli, Giovanni .
Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 1999, :288-293
[49]   Regression Optimization for System-level Production Control [J].
Phan, Dzung T. ;
Nguyen, Lam M. ;
Murali, Pavankumar ;
Pham, Nhan H. ;
Liu, Hongsheng ;
Kalagnanam, Jayant R. .
2021 AMERICAN CONTROL CONFERENCE (ACC), 2021,
[50]   System-level power optimization: Techniques and tools [J].
Benini, L ;
De Micheli, G .
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2000, 5 (02) :115-192