The Belle II Pixel Detector Data Acquisition and Reduction System

The upcoming Belle II experiment is designed to work at a luminosity of 8 x 10(35) cm(-2) s(-1), 40 times higher than its predecessor. The pixel detector of Belle II with its similar to 8 million channels will deliver ten times more data than all other sub-detectors together. A data rate of 22 Gbytes/s is expected for a trigger rate of 30 kHz and an estimated pixel detector occupancy of 3 %, which is by far exceeding the specifications of the Belle II event builder system. Therefore a realtime data reduction of a factor >30 is needed. A hardware platform capable of processing this amount of data is the ATCA based Compute Node (CN). Each CN consists of an xTCA carrier board and four AMC/mu TCA daughter-boards. The carrier board supplies the high bandwidth connectivity to the other CNs in the shelf via Rocket-IO links. In the current prototype design, each AMC board is equipped with a Xilinx Virtex5FX70T FPGA, 4 GB of memory, Gbit Ethernet and two bi-directional optical links allowing for high data transfer rates. IPMI control of mother-and daughter-board is foreseen. One ATCA shelf containing 10 motherboards/40 daughter-boards is sufficient to process the data from the 40 front end boards. The data reduction on the CN is done in two steps. First, the data delivered by the front end electronics via optical links has to be stored in memory until the high level trigger (HLT) decision has been made. This might take, depending on the event topography, up to seconds. This decreases the event rate by a factor >3. In a second step, pixel data of positively triggered events is reduced with the help of regions of interest (ROI), calculated by the HLT from projecting trajectories back to the pixel detector plane. The design allows additional ROI inputs computed from SVD tracklet data as well as from hit cluster properties. The final data reduction is achieved by sending only data within these ROIs to the main event builder.