Compaction of IDDQ test sequence using reassignment method

被引：1

作者：

Maeda, T ^{[1
]}

Kinoshita, K ^{[1
]}

机构：

[1] Osaka Univ, Dept Appl Phys, Osaka, Japan

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2000年 / 16卷 / 03期

关键词：

sequential circuit; IDDQ testing; test compaction; reassignment method; weighted random vector;

D O I：

10.1023/A:1008343431975

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.

引用

页码：243 / 249

页数：7

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