Through silicon vias filled with planarized carbon nanotube bundles

被引：46
作者：
Wang, Teng [1 ,2 ]
Jeppson, Kjell [1 ]
Olofsson, Niklas [3 ]
Campbell, Eleanor E. B. [4 ,5 ]
Liu, Johan [1 ,6 ,7 ]
机构：
[1] Chalmers Univ Technol, Dept Microtechnol & Nanosci, SE-41296 Gothenburg, Sweden
[2] SHT Smart High Tech AB, SE-42834 Kallered, Sweden
[3] Univ Gothenburg, Dept Phys, SE-41296 Gothenburg, Sweden
[4] Univ Edinburgh, Sch Chem, Edinburgh EH9 3JJ, Midlothian, Scotland
[5] Konkuk Univ, Dept Phys, Seoul 143701, South Korea
[6] Shanghai Univ, Sch Mech Engn & Automat, Key Lab New Displays & Syst Applicat, Shanghai 200072, Peoples R China
[7] Shanghai Univ, Sch Mech Engn & Automat, SMIT Ctr, Shanghai 200072, Peoples R China
来源：
NANOTECHNOLOGY | 2009年 / 20卷 / 48期
基金：
美国国家科学基金会; 瑞典研究理事会;
关键词：
THROUGH-SILICON; INTERCONNECTS; GROWTH;
D O I：
10.1088/0957-4484/20/48/485203
中图分类号：
TB3 [工程材料学];
学科分类号：
0805 ; 080502 ;
摘要：
The feasibility of using carbon nanotube (CNT) bundles as the fillers of through silicon vias (TSVs) has been demonstrated. CNT bundles are synthesized directly inside TSVs by thermal chemical vapor deposition (TCVD). The growth of CNTs in vias is found to be highly dependent on the geometric dimensions and arrangement patterns of the vias at atmospheric pressure. The CNT-Si structure is planarized by a combined lapping and polishing process to achieve both a high removal rate and a fine surface finish. Electrical tests of the CNT TSVs have been performed and their electrical resistance was found to be in the few hundred ohms range. The reasons for the high electrical resistance have been discussed and possible methods to decrease the electrical resistance have been proposed.
引用
收藏
页数：6
相关论文
共 50 条
  • [41] Superconformal Nickel Deposition in Through Silicon Vias: Experiment and Prediction
    Braun, T. M.
    Kim, S-H
    Lee, H-J
    Moffat, T. P.
    Josell, D.
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2018, 165 (07) : D291 - D300
  • [42] Passive Equalizer Design for Through Silicon Vias with Perfect Compensation
    Sun, Ruey-Bo
    Wen, Chang-Yi
    Wu, Ruey-Beei
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (11): : 1815 - 1822
  • [43] An Analytical Model for High-Frequency Through Silicon Vias
    Gharib, Mohamed Adel
    Abdelzaher, Salma
    Partin-Vaisband, Inna
    PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, 2024, : 282 - 286
  • [44] Thermally induced void growth in through-silicon vias
    Kong, Lay Wai
    Lloyd, James R.
    Rudack, Andrew C.
    Diebold, Alain C.
    JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2013, 12 (02):
  • [45] An Analytical Model for Capacitance of Silicon-Insulator-Silicon Through- Silicon- Vias
    Li, Bohao
    Li, An'an
    Xiong, Miao
    Yang, Jianxun
    Chen, Zhiming
    Ding, Yingtao
    2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 1464 - 1468
  • [46] A Novel Cu Plating Formula for Filling Through Silicon Vias
    Shen, Shao-Ping
    Dow, Wei-Ping
    Kubo, Motonobu
    Kamitamari, Tohru
    Cheng, Eric
    Lin, Jing-Yuan
    Hsu, Fu-Chiang
    IMPACT: 2009 4TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE, 2009, : 166 - +
  • [47] Study on the noise coupling and shielding between through silicon vias
    Liu, Huan
    Fang, Runiu
    Miao, Min
    Jin, Yufeng
    2019 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL AND POWER INTEGRITY (EMC+SIPI), 2019, : 394 - 399
  • [48] Carbon nanotube bundles with tensile strength over 80 GPa
    Bai, Yunxiang
    Zhang, Rufan
    Ye, Xuan
    Zhu, Zhenxing
    Xie, Huanhuan
    Shen, Boyuan
    Cai, Dali
    Liu, Bofei
    Zhang, Chenxi
    Jia, Zhao
    Zhang, Shenli
    Li, Xide
    Wei, Fei
    NATURE NANOTECHNOLOGY, 2018, 13 (07) : 589 - +
  • [49] Simple Formula for the Internal Impedance of Mixed Carbon Nanotube Bundles
    Lu, Qijun
    Zhu, Zhangming
    Yang, Yintang
    Yin, Xiangkun
    Liu, Xiaoxian
    Qu, Chenbing
    Liu, Yang
    2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
  • [50] Vertical delay modeling of copper/carbon nanotube composites in a tapered through silicon via
    Rao, Madhav
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 80 - 85
12345