Assessment of Circuit Optimization Techniques Under NBTI

被引:15
作者
Chen, Xiaoming [1 ]
Wang, Yu [1 ]
Yang, Huazhong [2 ]
Cao, Yu [3 ]
Xie, Yuan [4 ]
机构
[1] Tsinghua Univ, Dept EE, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Dept Elect Engn, Cheung Kong Scholars Program, Beijing 100084, Peoples R China
[3] Arizona State Univ, Tempe, AZ 85287 USA
[4] Penn State Univ, University Pk, PA 16802 USA
基金
中国国家自然科学基金;
关键词
LEAKAGE POWER; AWARE; RELIABILITY; LIFETIME;
D O I
10.1109/MDAT.2013.2266651
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A study conducts a comprehensive investigation on existing circuit optimization techniques against NBTI, degradation mechanism that has become a critical reliability issue for nano-scaled IC design. These techniques are categorized by their intrinsic characteristics and several important observations are made to give design guideline on NBTI mitigation. It is demonstrated that NBTI-aware circuit optimization techniques can be either compensation techniques or mitigation techniques. The two categories focus on reducing different parts of circuit delay and they have different efficiency, overheads, and complexity. All the optimization techniques tune electrical parameters which are easy to adjust, such as supply voltage, threshold voltage, and stress time. A popular physical origin of NBTI is the reaction-diffusion (R-D) mechanism where NBTI is described as the generation of charges in the Si/oxide interface.
引用
收藏
页码:40 / 49
页数:10
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