Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

This paper presents a simple and low-cost 3-D process technology for the wafer-level packaging (WLP) of microelectromechanical system (MEMS) devices. A small-sized WLP (1.0 x 1.0 x 0.35 mm) with a hermetically sealed cavity for the moving parts of MEMS devices was fabricated by using specially designed processes. The WLP was developed using three key techniques: through-wafer interconnection, wafer bonding, and bilateral face-MEMS fabrication. The expense and complexity of processes such as silicon deep reactive ion etching and electroplating that arise from bilateral processing for through-wafer interconnection were overcome by using bulk micromachining technology. The fabricated WLP chips with a bonding area of 0.314 mm(2) showed an average shear strength of 9.74 kg/mm(2) and a leak rate less than 7 x 10(-10) mbar.cc/sec. In addition, the chips had less than 0.1 dB insertion loss before and after reliability testing. This newly developed 3-D process technology is a good candidate for WLP MEMS fabrication because it is simple and cost-effective.