A test generation framework for quantum cellular automata circuits

被引:31
作者
Gupta, Pallav [1 ]
Jha, Niraj K.
Lingappan, Loganathan
机构
[1] Princeton Univ, Dept Elect Engn, Princeton, NJ 08544 USA
[2] NVIDIA Corp, Santa Clara, CA 95050 USA
基金
美国国家科学基金会;
关键词
computer-aided design (CAI)) for nanotechnologies; quantum cellular automata (QCA); test generation; MULTIPLE-FAULT-DETECTION; LOGIC; DESIGN;
D O I
10.1109/TVLSI.2007.891081
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we present a test generation framework for quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted recent significant attention and shows promise as a viable future technology. This work is motivated by the fact that the stuck-at fault test set of a circuit is not guaranteed to detect all defects that can occur in its QCA implementation. We show how to generate additional test vectors to supplement the stuck-at fault test set to guarantee that all simulated defects in the QCA gates get detected. Since nanotechnologies will be dominated by interconnects, we also target bridging faults on QCA interconnects. The efficacy of our framework is established through its application to QCA implementations of MCNC and ISCAS'85 bench-marks that use majority gates as primitives.
引用
收藏
页码:24 / 36
页数:13
相关论文
共 27 条
[1]   Demonstration of a six-dot quantum cellular automata system [J].
Amlani, I ;
Orlov, AO ;
Snider, GL ;
Lent, CS ;
Bernstein, GH .
APPLIED PHYSICS LETTERS, 1998, 72 (17) :2179-2181
[2]   Digital logic gate using quantum-dot cellular automata [J].
Amlani, I ;
Orlov, AO ;
Toth, G ;
Bernstein, GH ;
Lent, CS ;
Snider, GL .
SCIENCE, 1999, 284 (5412) :289-291
[3]  
Beckett P., 2002, ASIA PACIFIC C COMPU, P141
[4]   A memory design in QCAs using the SQUARES formalism. [J].
Berzon, D ;
Fountain, TJ .
NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS, 1999, :166-169
[5]  
GERGEL N, 2003, P ACM GREAT LAK S VL, P60
[6]  
GOEL P, 1981, IEEE T COMPUT, V30, P215, DOI 10.1109/TC.1981.1675757
[7]   Clocking of molecular quantum-dot cellular automata [J].
Hennessy, K ;
Lent, CS .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (05) :1752-1755
[9]  
Jha N. K., 2003, Testing of Digital Systems
[10]   Multiple fault detection in fan-out free circuits using minimal single fault test set [J].
Lai, K ;
Lala, PK .
IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (06) :763-765