Carrier transport in nanodevices

Future VLSI scaling realization of gate lengths is expected to 70 nm and below. While we do not know all the underlying physics, we are beginning to understand some limiting factors; which include quantum transport, in these structures. The discrete nature of impurities, the fact that devices have critical lengths comparable to their coherence lengths, and size quantization will all be important in these structures. These phenomena will lead to pockets of charge, which will appear as coupled quantum dots in the device transport. We review some of the physics of these dots.