Overcoming Variations in Nanometer-Scale Technologies

被引：45
作者：
Sapatnekar, Sachin S. [1 ]
机构：
[1] Univ Minnesota, Dept Elect & Comp Engn, Minneapolis, MN 55455 USA
来源：
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS | 2011年 / 1卷 / 01期
基金：
美国国家科学基金会;
关键词：
On-chip sensors; power supply variations; process variations; thermally aware design; thermal variations; STATISTICAL TIMING ANALYSIS; PARAMETRIC YIELD ESTIMATION; NON-GAUSSIAN PARAMETERS; GATE OXIDE; LEAKAGE POWER; CRITICALITY COMPUTATION; GENERAL FRAMEWORK; 3D ICS; DESIGN; RELIABILITY;
D O I：
10.1109/JETCAS.2011.2138250
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and environmental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.
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收藏
页码：5 / 18
页数：14
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