DC Noise Margin and Failure Analysis of Proposed Low Swing Voltage SRAM cell for High Speed CMOS Circuits

This paper focuses on the DC noise margin analysis and read/write failure analysis of the proposed 8T low power SRAM cell. In the proposed structure two voltage sources, one connected with the Bit line and the other connected with the Bit bar line for reducing the voltage swing during the switching activity. These two extra voltage sources will control the voltage swing on the output node and improve the stability. DC noise margin has been calculated by using loop gain technique and comparison made with that of conventional 6T SRAM justify the efficacy of the superiority of the proposed SRAM structure. Read and Write failure analyses are also done by using Monte-Carlo simulation. Simulation has been done in 65nm CMOS technology with 1 volt of power supply. Analog and schematic simulations have been done in 65nm environment with the help of Microwind 3.1 by using BSimM4 model.