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- [1] A Gate Driver Design for Medium Voltage Silicon Carbide Power Devices with High dv/dt IECON 2018 - 44TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2018, : 877 - 882
- [2] A Gate-Driver Architecture with High Common-Mode Noise Immunity under Extremely High dv/dt 2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021), 2021, : 2532 - 2536
- [4] Induced Gate-Source Voltage Mechanism and Gate Driver Design in All-SiC PWM Rectifier with Ultra-High Voltage Slew Rate (dv/dt) 2020 IEEE 9TH INTERNATIONAL POWER ELECTRONICS AND MOTION CONTROL CONFERENCE (IPEMC2020-ECCE ASIA), 2020, : 1863 - 1867
- [6] dv/dt Noise canceling circuit in ultra-high-voltage MOS gate drivers Analog Integrated Circuits and Signal Processing, 2013, 77 : 271 - 276
- [8] Improving Voltage Sensor Noise Immunity in a High Voltage and High dv/dt Environment 2020 THIRTY-FIFTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2020), 2020, : 107 - 113
- [10] Advanced gate driver for IGBT devices with dv/dt and peak voltage limitation based on active gate-emitter voltage control 2016 18TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'16 ECCE EUROPE), 2016,