Twin SONOS memory with-30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process

By manipulating the charge profile through the inverted sidewall patterning on the channel, stable 2-bit operation in silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory with sub-90-nm gate length can be achieved. The fabricated memory cell his about 30-nm twin Oxide-Nitride-Oxide-Silicon physically separated by the inverted sidewall patterning method under the same control gate based on damascene gate process. Comparing with a conventional single SONOS memory (SSM), this novel twin SONOS memory cell can maintain the better control of trapped charge distribution due to the strong diffusion barrier of charges. As a result, better endurance, retention, and erase speed than SSM can be obtained in the short (sub-100-nm) gate length devices.