A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET

被引:19
|
作者
Narendar, Vadthiya [1 ]
Rai, Saurabh [1 ]
Tiwari, Siddharth [1 ]
机构
[1] MNNIT, Dept Elect & Commun Engn, Allahabad 211004, Uttar Pradesh, India
关键词
Drain-induced barrier lowering (DIBL); Dualmaterial double-gate (DMDG); FinFET; Short-channel effects (SCEs); Subthreshold current; Underlap; SOI MOSFETS; METAL GATE; CMOS TECHNOLOGY; TRANSISTORS; DESIGN; SI;
D O I
10.1007/s10825-016-0899-x
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are regarded as leading front-runners in the semiconductor industry. To alleviate the short-channel effects (SCEs) in the DG MOSFET, a new underlap dual-material (DM) DG FinFET device structure is proposed herein, combining the advantages of an underlapped device with those of a dual-material gate (DMG) device. Two-dimensional (2D) analytical surface potential and subthreshold current modelling of the proposed device has been done by solving Poisson's equation. It has been found that the results obtained analytically are in good agreement with numerical simulation results. As the underlap length () is increased, a substantial reduction of the subthreshold current due to enhanced gate control over the channel regime is observed. The DMG used in the structure improves the average velocity of the carriers, which leads to superior drive current for the device. The proposed device structure is compared with underlap single-material (SM) DG FinFET structure in terms of electrical characteristics, such as drain-induced barrier lowering (DIBL). This comparison confirms the suppression of SCEs with increasing in both structures, being more significant in the case of the underlap DMDG FinFET.
引用
收藏
页码:1316 / 1325
页数:10
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