Effect of Grain Boundary Protrusion on Electrical Performance of Low Temperature Polycrystalline Silicon Thin Film Transistors

被引：23
作者：
Billah, Mohammad Masum [1 ,2 ]
Siddik, Abu Bakar [1 ,2 ]
Kim, Jung Bae [3 ]
Zhao, Lai [3 ]
Choi, Soo Young [3 ]
Yim, Dong Kil [3 ]
Jang, Jin [1 ,2 ]
机构：
[1] Kyung Hee Univ, Adv Display Res Ctr, Seoul 2447, South Korea
[2] Kyung Hee Univ, Dept Informat Display, Seoul 02447, South Korea
[3] Appl Mat Inc, AKT Display, Santa Clara, CA 95054 USA
来源：
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | 2019年 / 7卷 / 01期
关键词：
Low temperature polycrystalline silicon (LTPS); thin-film transistors (TFTs); technology computer-aided design (TCAD); SEQUENTIAL LATERAL SOLIDIFICATION; POLYSILICON TFT; OUTPUT CHARACTERISTICS; SIMULATION; RELIABILITY; FABRICATION; STATES; MODEL;
D O I：
10.1109/JEDS.2019.2911088
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We studied the impact of grain boundary (GB) protrusion on the electrical properties of low temperature polycrystalline silicon thin film transistors. The analysis of atomic force microscopy and transmission electron microscopy images indicate the grain size of similar to 350 nm and a protrusion height of similar to 35 nm. The transfer and output characteristics are well fitted by technology computer-aided design using two different density of states for poly-Si grain and GB, respectively. From 2-D contour mapping, a drastic reduction of hole concentration (similar to 5x10(16) cm(-3)) at GB protrusion site was obtained as compared to the grain (similar to 3 x 10(18) cm(-3)). Trapping concentration at GB is much higher, which leads to the reduction in the mobility.
引用
收藏
页码：503 / 511
页数：9
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