A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy

被引：9

作者：

Chou, Che-Wei ^{[1
]}

Huang, Yu-Jen ^{[2
]}

Li, Jin-Fu ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Tao Yuan 320, Taiwan

[2] Taiwan Semicond Mfg Co, Test Chip Design Dept, Hsinchu 310, Taiwan

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2013年 / 32卷 / 04期

关键词：

3-D integrated circuit (IC); 3-D random access memory (RAM); memory repair; memory testing; through-silicon-via (TSV); yield improvement; INFRASTRUCTURE IP; HIGH-DENSITY; DESIGN;

D O I：

10.1109/TCAD.2012.2222882

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs.

引用

页码：572 / 583

页数：12

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