A FPGA-based Hardware Accelerator for Multiple Convolutional Neural Networks

Convolution Neural Network (CNN) has been widely used in many computer vision tasks. Due to the rapid growth of CNN, the accelerator that only supports single network could not meet the requirement of application. Based on the work of ZynqNet, which is a dedicated CNN accelerator, in this paper, we propose a FPGA-based CNN accelerator which supports the acceleration of multiple networks, and present an automatic mapping flow in which users only need to provide network description files and test image to accelerate a specified network. And we adopt a dynamic fixed-point quantization strategy to reduce resource consumption. Experimental results shows the performance density and power efficiency of our design can reach 0.054GOPS/DSP and 5.24GOPS/W respectively when accelerating SqueezeNet.