An Output-Capacitorless Low -Dropout Regulator with-132dB PSRR at 1KHz

This paper presents an output-capacitorless low-dropout (LDO) regulator with with-132dB power supply rejection ratio (PSRR) at 1KHz. By using a Rising-Class-A voltage buffer, the non-dominant parasitic poles can be pushed to higher frequencies and leads to good stability in power supply rejection ratio (PSRR) performance. The proposed circuit is designed with 0.18-mu m CMOS process technology. The circuit are verified with a 1.8V power supply. From the simulation results, the proposed regulator delivers a 100mA maximum load current with a dropout voltage less than 200mV. The simulated PSRR of the proposed output-capacitorless LDO regulator reached-132dB at 1KHz. Moreover, the circuit has 32 mu A quiescent current and can settle within 0.5 mu s.