BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

被引:73
|
作者
Khandelwal, Sourabh [1 ]
Chauhan, Yogesh Singh [2 ]
Lu, Darsen D. [2 ]
Venugopalan, Sriramkumar [2 ]
Ul Karim, Muhammed Ahosan [2 ]
Sachid, Angada Bangalore [2 ]
Nguyen, Bich-Yen [3 ]
Rozeau, Olivier [4 ]
Faynot, Olivier [4 ]
Niknejad, Ali M. [2 ]
Hu, Chenming Calvin [2 ]
机构
[1] Norwegian Univ Sci & Technol, Dept Elect & Telecommun, N-7034 Trondheim, Norway
[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
[3] Soitec, Peabody, MA 01960 USA
[4] CEA, LETI, F-38054 Grenoble, France
关键词
BSIM-IMG; compact modeling; FDSOI MOSFETs; ultrathin-body silicon-on-insulator (UTBSOI) MOSFETs; THRESHOLD VOLTAGE; CHARGE; INVERSION;
D O I
10.1109/TED.2012.2198065
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.
引用
收藏
页码:2019 / 2026
页数:8
相关论文
共 16 条
  • [1] Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX
    Ohata, A.
    Bae, Y.
    Fenouillet-Beranger, C.
    Cristoloveanu, S.
    IEEE ELECTRON DEVICE LETTERS, 2012, 33 (03) : 348 - 350
  • [2] BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion
    Agarwal, H.
    Kushwaha, P.
    Dasgupta, A.
    Y-Kao, M.
    Morshed, T.
    Workman, G.
    Shanbhag, K.
    Li, X.
    Vinothkumar, V.
    Chauhan, Y. S.
    Salahuddin, S.
    Hu, C.
    2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020), 2020,
  • [3] Symmetric BSIM-SOI-Part I: A Compact Model for Dynamically Depleted SOI MOSFETs
    Dabhi, Chetan Kumar
    Rajasekharan, Dinesh
    Pahwa, Girish
    Nandi, Debashish
    Karumuri, Naveen
    Turuvekere, Sreenidhi
    Dutta, Anupam
    Swaminathan, Balaji
    Srihari, Srikanth
    Chauhan, Yogesh S.
    Salahuddin, Sayeef
    Hu, Chenming
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (04) : 2284 - 2292
  • [4] Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs
    Lin, Yen-Kai
    Kushwaha, Pragya
    Agarwal, Harshit
    Chang, Huan-Lin
    Duarte, Juan Pablo
    Sachid, Angada B.
    Khandelwal, Sourabh
    Salahuddin, Sayeef
    Hu, Chenming
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (10) : 3986 - 3990
  • [5] Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control
    Fasarakis, Nikolaos
    Karatsori, Theano
    Tassis, Dimitrios H.
    Theodorou, Christoforos G.
    Andrieu, Francois
    Faynot, Olivier
    Ghibaudo, Gerard
    Dimitriadis, Charalabos A.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (04) : 969 - 975
  • [6] A study of the threshold voltage variations for ultrathin body double gate SOI MOSFETs
    Tang, CS
    Lo, SC
    Lee, JW
    Tsai, JH
    Li, YM
    NSTI NANOTECH 2004, VOL 3, TECHNICAL PROCEEDINGS, 2004, : 145 - 148
  • [7] Impact of Back-Gate Biasing on the Transport Properties of 22 nm FD-SOI MOSFETs at Cryogenic Temperatures
    Al Mamun, Fahad
    Vasileska, Dragica
    Esqueda, Ivan Sanchez
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (10) : 5417 - 5423
  • [8] Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs
    Svilicic, B.
    Jovanovic, V.
    Suligoj, T.
    SOLID-STATE ELECTRONICS, 2009, 53 (05) : 540 - 547
  • [9] Reduction in threshold voltage fluctuation in fully-depleted SOI MOSFETs with back gate control
    Numata, T
    Noguchi, M
    Takagi, S
    SOLID-STATE ELECTRONICS, 2004, 48 (06) : 979 - 984
  • [10] Silicide as diffusion source for dopant segregation in 70-nm MOSFETs with PtSi Schottky-barrier source/drain on ultrathin-body SOI
    Qiu, Z. J.
    Zhang, Z.
    Lu, J.
    Liu, R.
    Ostling, M.
    Zhang, S. -L.
    ULIS 2008: PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON, 2008, : 23 - +