共 43 条
[1]
[Anonymous], 2011, INT TECHNOLOGY ROADM
[3]
Process Solutions and Polymer Materials for 3D-WLP Through Silicon Via Filling
[J].
2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC),
2010,
:1696-1698
[4]
Che F.X., 2011, P IEEE INT 3D SYST I, P1
[5]
Civale Y., 2010, IEEE 3D SYST INT C 3, P1, DOI DOI 10.1109/3DIC.2010.5751482
[6]
3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2011, 1 (06)
:833-840
[9]
Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications
[J].
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY,
2011, 1 (06)
:825-832
[10]
<bold>Multi-Level Cu Interconnects Integration and Characterization with Air Gap as Ultra-Low K Material Formed using a Hybrid Sacrificial Oxide / Polymer Stack</bold>
[J].
PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE,
2007,
:58-+