Analysis of the Extra Delay on Interconnects Caused by Resistive Opens and Shorts

被引：2

作者：

Maqueda, Pablo ^{[1
]}

Rius, Josep ^{[1
]}

机构：

[1] Univ Politecn Cataluna, Dept Elect Engn, E-08028 Barcelona, Spain

来源：

2009 15TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM | 2009年

关键词：

EXPRESSIONS; CROSSTALK;

D O I：

10.1109/IOLTS.2009.5196016

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents an analytical solution for the delay introduced by opens and shorts on RC interconnects. Starting from the set of PDEs that defines the dynamics of such lines, complete solutions are found. Compact expressions for the delay, derived from the complete solutions, show an excellent agreement when compared with simulations, for realistic values of interconnect parameters, driver resistance and an arbitrary values and place of the defect. This information is useful for testing of such interconnects.

引用

页码：208 / 209

页数：2

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