46% Peak PAE 28 GHz High Linearity Stacked-FET Power Amplifier IC with a Novel Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS

This paper presents a 28 GHz high linearity power amplifier (PA) IC with a novel two-step adaptively controlled bias circuit for 5th generation (5G) mobile terminal applications in a 45-nm silicon on insulator (SOI) CMOS process. The novel bias circuit adaptively controls the gate voltage of a stacked-FET by a step procedure to improve the 1dB compression point (P1dB) and efficiency in the several-dB backoff region. The PA employs a 3-stacked-FET structure to overcome the low breakdown voltage issue in scaled MOSFETs. At a supply voltage of 3.5 V, the fabricated PA exhibits a peak power added efficiency (PAE) of 46.0%, a saturated output power of 20.5 dBm, a 3 dB output power back-off efficiency of 35.2%, a 6 dB output power back-off efficiency of 26.0% and a small signal gain of 15.0 dB. The PA IC occupies only 0.23 mm(2).