Die stacking technology for terabit chip-to-chip communications

被引：8

作者：

Rahman, Arifur ^{[1
]}

Trezza, John ^{[2
]}

New, Bernie ^{[1
]}

Trimberger, Steve ^{[1
]}

机构：

[1] Xilinx Res Labs, 2100 Log Dr, San Jose, CA 95124 USA

[2] Cubic Wafer Inc, Merrimack, NH 03054 USA

来源：

PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2006年

关键词：

D O I：

10.1109/CICC.2006.320826

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a die stacking technology, leveraging on through die via (TDV) integration and wafer bonding, is presented. Using state-of-the-art volume manufacturing environment, 10:1 aspect ratio TDV and wafer-level bonding technology are developed and initial electrical and reliability characterization results of TDVs are provided. The opportunities for die-stacking technology to alleviate chip-to-chip communication bottleneck are discussed and visions for stacked-die applications, utilizing a programmable virtual backplane, are presented.

引用

页码：587 / 590

页数：4

共 8 条

[1] 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration [J].

Banerjee, K ;

Souri, SJ ;

Kapur, P ;

Saraswat, KC .

PROCEEDINGS OF THE IEEE, 2001, 89 (05) :602-633

[2]

BURNS J, 2001 ISSCC, P268

[3] Interconnect limits on gigascale integration (GSI) in the 21st century [J].

Davis, JA ;

Venkatesan, R ;

Kaloyeros, A ;

Beylansky, M ;

Souri, SJ ;

Banerjee, K ;

Saraswat, KC ;

Rahman, A ;

Reif, R ;

Meindl, JD .

PROCEEDINGS OF THE IEEE, 2001, 89 (03) :305-324

[4]

IEONG M, P 2003 CICC, P207

[5]

KAMON M, 1994, IEEE T MTT, V42

[6] Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].

Knickerbocker, JU ;

Andry, PS ;

Buchwalter, LP ;

Deutsch, A ;

Horton, RR ;

Jenkins, KA ;

Kwark, YH ;

McVicker, G ;

Patel, CS ;

Polastre, RJ ;

Schuster, C ;

Sharma, A ;

Sri-Jayantha, SM ;

Surovic, CW ;

Tsang, CK ;

Webb, BC ;

Wright, SL ;

McKnight, SR ;

Sprogis, EJ ;

Dang, B .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753

[7] Cellular handset integration - SIP versus SOC [J].

Krenik, W ;

Buss, DD ;

Rickert, P .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (09) :1839-1846

[8] Fabrication technologies for three-dimensional integrated circuits [J].

Reif, R ;

Fan, A ;

Chen, KN ;

Das, S .

PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2002, :33-37

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