INVITED: RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

被引：0

作者：

Park, Hee Chun ^{[1
]}

Chang, Kyungwook ^{[1
]}

Ku, Bon Woong ^{[1
]}

Kim, Jinwoo ^{[1
]}

Lee, Edward ^{[1
]}

Kim, Daehyun ^{[1
]}

Chaudhuri, Arjun ^{[2
]}

Banerjee, Sanmitra ^{[2
]}

Mukhopadhyay, Saibal ^{[1
]}

Chakrabarty, Krishnendu ^{[2
]}

Lim, Sung Kyu ^{[1
]}

机构：

[1] Georgia Inst Technol, Dept Elect & Comp Engn, Atlanta, GA 30332 USA

[2] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27706 USA

来源：

PROCEEDINGS OF THE 2019 56TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2019年

关键词：

D O I：

10.1145/3316781.3323486

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Monolithic 3D IC overcomes the limitation of the existing through-silicon-via (TSV) based 3D IC by providing denser vertical connections with nano-scale inter-layer vias (ILVs). In this paper, we demonstrate a thorough RTL-to-GDS design flow for monolithic 3D IC, which is based on commercial 2D place-and-route (P&R) tools and clever ways to extend them to handle 3D IC designs and simulations. We also provide a low-cost built-in-self-test (BIST) method to detect various faults that can occur on ILVs. Lastly, we present a resistive random access memory (ReRAM) compiler that generates memory modules that are to be integrated in monolithic 3D ICs.

引用

页数：4