Write strategies for 2 and 4-bit multi-level phase-change memory

被引：208

作者：

Nirschl, T. ^{[1
,2
]}

Philipp, J. B. ^{[3
]}

Flapp, T. D. ^{[3
]}

Burr, G. W. ^{[5
,7
]}

Rajendran, B. ^{[4
]}

Leeo, M. -H. ^{[6
]}

Schrott, A. ^{[4
]}

Yang, M. ^{[4
]}

Breitwisch, M. ^{[4
]}

Chen, C. -F ^{[6
]}

Joseph, E. ^{[4
]}

Lamorey, M.

Cheek, R.

Chen, S. -H

Zaidi, S. ^{[3
]}

Raoux, S. ^{[7
]}

Chen, Y. C. ^{[6
]}

Zhu, Y.

Bergmann, R.

Lung, H. -L. ^{[6
]}

Lam, C.

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, IBM Qimonda Macronix PCRAM Joint Project, Yorktown Hts, NY 10598 USA

[2] Infineon Technol, Neubiberg, Germany

[3] Qimonda, Munich, Germany

[4] IBM Corp, Yorktown Hts, NY USA

[5] IBM Corp, Essex Jct, VT USA

[6] Macronix Int Co Ltd, Hsinchu, Taiwan

[7] IBM Corp, San Jose, CA USA

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418973

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using a novel integration scheme, a test array at 4bits/cell and a 32kb memory page at 2bits/cell are experimentally demonstrated.

引用

页码：461 / +

页数：2