On-chip Delay Measurement Circuit for Reliability Characterization of SRAM

This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available. 1KB SRAM is used as test setup for which on-chip read access time measurement is performed. On-chip delay measurement is performed using proposed novel architecture of 2-stage multi-resolution based vernier time-to-digital converter (TDC). TDC is designed for 2 ps resolution. Actual architecture of TDC is 5 bit, however entire range can be shifted with minimum steps of 40 ps to achieve desirable range. A novel design of programmable linear delay element (PLDE) is also presented in this paper, which is used as a key component of the TDC architecture. Two types of PLDEs are designed to provide delay with step size 2 ps and 40 ps. Use of PLDE in TDC architecture provides the facility of adjustment which makes it more robust to process and temperature variations. Overall design is laid out in 65nm CMOS process and evaluated using post layout simulation.