A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits

This paper presents a physics-based semiempirical model of drain saturation voltage (V-DS,V- SAT) of a FinFET device suitable for analog circuit design. The previous belief of similarity of the saturation phenomenon in the FinFET and planar MOSFET devices is investigated for the first time and is shown to be inconsistent in the FinFET device. When the value of VDS is increased to VDS, SAT, then at a critical point, the product of electron density (n) and electron velocity (v(d)) starts decreasing at the silicon-dielectric interface while it increases at the mid of the fin. This critical point lies within the drain extension (DE) region near to channel-DE junction. It is also observed that VDS, SAT increases linearly with VGS (>= 0.6 V). Based on this, a semiempirical V-DS, SAT model is proposed, which is simple enough to be usable in analog circuit design. Moreover, compared to planar devices, a strikingly different trend of the output resistance (r(o)) in FinFET is observed. We explained this behavior for the first time using our understanding of FinFET saturation phenomenon. By employing our semiempirical model of V-DS, SAT and the trend of ro with V-DS, we estimated the bias voltages of the FinFET amplifier to improve the gain by about 3x while not increasing the power dissipation. Since the gains of cascode and telescopic cascode amplifiers are strongly dependent on ro, these FinFET amplifiers can be designed to have much smaller overdrive voltages compared to its planar counterparts.