A Design Scheme for the Improved Non-binary LDPC Coder-decoder

Specific to the problem that the low coding and decoding efficiency and the large resources occupation existed in the non-binary LDPC coder-decoder based on FPGA, this paper proposed an improvement plan that can effectively improve the coding and decoding efficiency and decrease the resources occupation of FPGA. Combining with QC-LDPC encoding algorithm and Mixed-FFT-BP decoding algorithm, the scheme can decrease the memory capacity when coding to improve the utilization ratio and decrease the usage of multiplier when decoding. This scheme can guarantee the data precision, in the meanwhile, decrease the loss of logical resources, which achieve the coder-decoder's optimal improvement. The theory research and simulation results demonstrate that Mixed-FFT-BP decoding algorithm can decrease the usage of multipliers, the loss of logical resources and the quantization error without the loss of precision in the case of ensuring accuracy of the data in the process of operation. This scheme is a practical scheme for coder-decoder, which can provide reference for its actual application.