共 50 条
- [1] Design of a 20 GHz Bandwidth Dual-stage Dual-FIR Channel Emulator 2015 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND SIGNAL INTEGRITY, 2015, : 148 - 153
- [2] A low-cost FPGA implementation of multi-channel FIR filter with variable bandwidth IEICE ELECTRONICS EXPRESS, 2015, 12 (22):
- [3] Implementation of a FIR filter by using CPLD Huaqiao Daxue Xuebao/Journal of Huaqiao University, 2001, 22 (01): : 76 - 79
- [4] FPGA Implementation of Symmetric Systolic FIR Filter using Multi-channel Technique PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON VLSI DEVICE, CIRCUIT AND SYSTEM (IEEE VLSI DCS 2020), 2020, : 225 - 228
- [5] Implementation considerations and performance comparison of variable bandwidth FIR filter and phase equalized IIR filter CONFERENCE RECORD OF THE FORTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1-5, 2007, : 1139 - +
- [7] FIR Digital Filter Implementation using flattened coefficient ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL III: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 363 - 366
- [9] A Review: FIR Filter Implementation 2017 2ND IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2017, : 137 - 141
- [10] Implementation of a FIR filter model using reversible Fredkin Gate 2014 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2014, : 690 - 694