Dynamically reconfigurable system-on-programmable-chip

Today's high-density FPGAs and intellectual property (IP) components enable the integration of complex systems in one programmable chip. New design strategies and concepts have to be developed in order to utilize the new system-level integration facilities. The approach introduced within this paper describes the implementation of a communication infrastructure that provides a number of on-chip IP-sockets. By using the FPGA-feature of partial dynamic reconfiguration, different IP components can be plugged into these sockets during runtime. This leads to a reconfigurable system that can be adapted to varying demands. In this context we designed a 32-bit RISC processor and an AMBA on-chip interconnection bus. Finally we mapped these components on a reconfigurable system-level FPGA. The resulting sizes and the utilization of the FPGA's resources are presented within the last part of this paper.