Hardware Implementation of Floating-point Operating Devices by Using IEEE-754 Binary Arithmetic Standard

Currently, in modern microprocessors, digital signal processors, mathematical coprocessors and other digital devices, arithmetic operations with floating-point numbers (FPN) are performed by using special hardware. This equipment is called a floating-point unit (FPU). The FPU is usually constructed by combining floating-point operating devices. In this paper, we consider operating devices for performing addition, subtraction, multiplication, and division of floating-point numbers using the IEEE-754 binary arithmetic standard. The algorithms for selected operations are also presented. These algorithms are specified in the implementation of floating-point operating devices in 32-bit and 64-bit IEEE-754 formats which are most commonly used in scientific computations. Circuit simulation of the considered devices was performed in the Altera Quartus-II CAD environment, and their hardware complexity and delay were evaluated. The reliability of selected operations was confirmed by the results of the timing diagrams obtained from the simulation.