Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell

被引：36

作者：

Osada, K ^{[1
]}

Shin, JL

Khan, M

Liou, Y

Wang, K

Shoji, K

Kuroda, K

Ikeda, S

Ishibashi, K

机构：

[1] Hitachi Ltd, Syst LSI Res Dept, Tokyo 1858601, Japan

[2] Hitachi Semicond Amer Inc, San Jose, CA 95134 USA

[3] Hitachi Ltd, Semicond & Integrated Circuits Grp, Tokyo, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 11期

关键词：

cache memory; low power; self-timing; SRAM cell; SRAM chips;

D O I：

10.1109/4.962296

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A universal-V-dd 32-kB four-way-set-associative embedded cache has been developed. A test cache chip was fabricated by using 0.18-mum enhanced CMOS technology, and it was found to continuously operate from 0.65 to 2.0 V Its operating frequency and power are from 120 MHz and 1.7 mW at 0.65 V to 1.04 GHz and 530 mW at 2.0 V The cache is based on two new circuit techniques: a voltage-adapted timing-generation scheme with plural dummy cells for the wider voltage-range operation, and use of a lithographically symmetrical cell for lower voltage operation.

引用

页码：1738 / 1744

页数：7