Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET

被引：23
|
作者：
Pon, Adhithan [1 ]
Tulasi, Kuralla Sivanaga Venkata Poorna [2 ]
Ramesh, R. [1 ]
机构：
[1] SASTRA Deemed Univ, Sch Elect & Elect Engn, Device Modeling Lab, Thanjavur 613401, India
[2] SASTRA Deemed Univ, Dept ECE, Thanjavur 613401, India
来源：
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2019年 / 102卷
关键词：
Asymmetric DGTFET; Dielectric modulation; Interface traps; Ambipolar behaviour; SUPPRESSION; DESIGN; TFET;
D O I：
10.1016/j.aeue.2019.02.007
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed. The effect of a donor (positive) and acceptor (negative) trap charges with various concentrations on the device d.c characteristics are studied. A comparative analysis has been performed between symmetric silicon dual gate tunnel field effect transistor (DG-TFET) and ADMDG-TFET (both Si and Si0.3Ge0.7) with matching dimensions in the presence/absence of interface trap charges. It is found that a shift in threshold voltage (V-th) and subthreshold swing (SS) degradation are observed due to the presence of interface traps in both devices. However, the ADMDG TFET is more immune to V-th shift and SS degradation by acceptor and donor interface traps compared to silicon DG TFET. Also, the ambipolar current in ADMDG TFET is more suppressed than the silicon DG TFET in the presence of trap charges. (C) 2019 Elsevier GmbH. All rights reserved.
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页码：1 / 8
页数：8
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