Electromigration Reliability of Redistribution Lines in Wafer-level Chip-Scale Packages

被引:0
作者
Lai, Yi-Shao [1 ]
Kao, Chin-Li [1 ]
Chiu, Ying-Ta [1 ]
Appelt, Bernd K. [2 ]
机构
[1] ASE Grp, 26 Chin 3rd Rd,Nantze Export Proc Zone, Kaohsiung 811, Taiwan
[2] ASE Grp, Sunnyvale, CA 94085 USA
来源
2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2011年
关键词
SOLDER JOINTS; INTERFACE;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Wafer-level chip-scale packages (WLCSPs) have become subject to the same drive for miniaturization as all electronic packages. The I/O count is increasing and ball pitch is shrinking at the expense of trace pitch and in turn, current densities are increasing. This leads to current crowding and Joule heating in the vicinity of solder joints and under bump metallurgy (UBM) structures where resistance values change significantly. These phenomena are responsible for structural damage of redistribution line (RDL)/UBM and UBM/solder interconnects due to ionic diffusion or electromigration. In this work, sputtered Al and electroplated Cu RDLs are examined and quantified by three-dimensional electrothermal coupling analysis. Results provide a guideline for estimating maximum allowable currents and electromigration lifetime.
引用
收藏
页码:326 / 331
页数:6
相关论文
共 18 条
[1]   Evidence of grain-boundary versus interface diffusion in electromigration experiments in copper damascene interconnects [J].
Arnaud, L ;
Berger, T ;
Reimbold, G .
JOURNAL OF APPLIED PHYSICS, 2003, 93 (01) :192-204
[2]   ELECTROMIGRATION IN THIN ALUMINUM FILMS ON TITANIUM NITRIDE [J].
BLECH, IA .
JOURNAL OF APPLIED PHYSICS, 1976, 47 (04) :1203-1208
[3]  
Burton B., 1970, Metal. Sci, V4, P215, DOI DOI 10.1179/MSC.1970.4.1.215
[4]   Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations [J].
Chen, Jiunn ;
Lai, Yi-Shao ;
Hsieh, Chueh-An ;
Hu, Chia Yi .
MICROELECTRONICS RELIABILITY, 2010, 50 (04) :522-527
[5]  
JEDEC Solid State Technology Association, 2003, JESD22 B111 BOARD LE
[6]   Electromigration reliability and morphologies of Cu pillar flip-chip solder joints with Cu substrate pad metallization [J].
Lai, Yi-Shao ;
Chiu, Ying-Ta ;
Chen, Jiunn .
JOURNAL OF ELECTRONIC MATERIALS, 2008, 37 (10) :1624-1630
[7]  
Lai YS, 2006, EL PACKAG TECH CONF, P582
[8]   Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages [J].
Lai, Yi-Shao ;
Kao, Chin-Li .
MICROELECTRONICS RELIABILITY, 2006, 46 (08) :1357-1368
[9]   Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis [J].
Lai, Yi-Shao ;
Kao, Chin-Li .
JOURNAL OF ELECTRONIC MATERIALS, 2006, 35 (05) :972-977
[10]   Electromigration Reliability of 96.5Sn-3Ag-0.5Cu Flip-Chip Solder Joints With Au/Ni/Cu or Cu Substrate Pad Metallization [J].
Lai, Yi-Shao ;
Chiu, Ying-Ta ;
Lee, Chiu-Wen .
JOURNAL OF ELECTRONIC PACKAGING, 2009, 131 (02) :0210021-0210025