Double-layered vertically integrated amorphous-In2Ga2ZnO7 thin-film transistor

被引：15

作者：

Rha, Sang Ho ^{[1
]}

Kim, Un Ki ^{[2
,3
]}

Jung, Jisim ^{[2
,3
]}

Hwang, Eun Suk ^{[2
,3
]}

Choi, Jung-Hae ^{[4
]}

Hwang, Cheol Seong ^{[1
,2
,3
]}

机构：

[1] Seoul Natl Univ, Grad Sch Convergence Sci & Technol, Dept Nano Sci & Technol, Suwon 443270, Kyonggi Do, South Korea

[2] Seoul Natl Univ, Dept Mat Sci & Engn, Seoul 151744, South Korea

[3] Seoul Natl Univ, Interuniv Semicond Res Ctr, WCU Hybrid Mat Program, Seoul 151744, South Korea

[4] Korea Inst Sci & Technol, Elect Mat Res Ctr, Seoul 136791, South Korea

来源：

APPLIED PHYSICS LETTERS | 2013年 / 103卷 / 18期

基金：

新加坡国家研究基金会;

关键词：

D O I：

10.1063/1.4827955

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Two serially connected and vertically integrated amorphous-In2Ga2ZnO7 thin film transistors (V-TFTs) with similar to 600 and 400-nm channel lengths were fabricated. Top and bottom V-TFTs showed well-behaved transfer characteristics with an I-on/I-off ratio of similar to 10(8) and a sub-threshold swing of similar to 0.6 V/dec., which are much improved results compared with the previous report on single-layer V-TFTs. Electrical performances of two V-TFTs were cross-checked, and they showed certain influences from the other device depending on operation conditions, which was attributed to charge trapping in the gate dielectric layer during gate voltage sweeping. V-TFT with thermally grown SiO2 showed negligible charge trapping behavior. (C) 2013 AIP Publishing LLC.

引用

页数：5

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