Phase-locked loop with dual phase frequency detectors for high-frequency operation and fast acquisition

被引：9
|
作者：
Woo, YS [1 ]
Jang, YM [1 ]
Sung, MY [1 ]
机构：
[1] Korea Univ, Dept Elect Engn, Semicond & CAD Lab, Sungbuk Ku, Seoul 136701, South Korea
来源：
MICROELECTRONICS JOURNAL | 2002年 / 33卷 / 03期
关键词：
dual phase frequency detectors; phase-locked loop; high frequency; fast acquisition; low jitter; CMOS;
D O I：
10.1016/S0026-2692(01)00155-0
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The sequential phase frequency detector (PFD) has an unlimited error detection range and the precharge PFD has one and a half times better resolution performance than the sequential PFD. Therefore, by selective operation of the appropriate PFD connected to the well-adjusted charge pump, an unlimited error detection range, a high-frequency operation. and a higher speed lock-up time can be achieved. In this paper, we propose a phase-locked loop (PLL) with dual PFDs in which advantages of both PFDs can be combined. This structure can improve the tradeoff between acquisition behavior and locked behavior. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：245 / 252
页数：8
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