Aggressively scaled P-channel mosfets with stacked nitride-oxide-nitride, N/O/N, gate dielectrics

Ultrathin (tox,eq < 2.0 nm) Si3N4/SiO2 (hereafter N/O) gate dielectrics with improved interface characteristics compared to devices with thermal oxides have been formed by remote plasma enhanced CVD of Si3N4 Onto oxides. If the Si-SiO2 interface is intentionally nitrided prior to the Si3N4 deposition, the increased physical thickness of the N/O stack combined with the interfacial nitridation reduces the direct tunneling current by more than two orders of magnitude. The ensuing device structure can then be characterized as N/O/N. The top nitride layer is also an effective boron diffusion barrier improving short channel characteristics in p(+)-poly PMOSFETs. In addition, nitrogen can also be transported to the silicon/dielectric interface during post-deposition RTAs, and this reduces degradation of transconductance during hot carrier stressing.