Assertion-Based Verification for SoC Models and Identification of Key Events

The design of today's systems on chip (SoC's) raises difficult issues, in particular regarding verification. In their early design phases, hardware/software embedded systems are commonly described as ESL (Electronic System Level) models, such that their functional and transactional behavior can be analyzed by simulation. To enhance this validation process, we have previously developed a framework for the runtime verification of temporal properties formalized in PSL. After recalling its main features, we analyze its practicability with a variety of use cases. We also describe a recent improvement that enables the identification of key events during the evaluation of assertions, to ease both coverage analysis and system debug.