Towards Yield Improvement for AI Accelerators: Analysis and Exploration

At the manufacturing stage of AI chips, some fabrication faults are very critical since they significantly affect the accuracy of the executed AI workload. To detect these functionally critical faults, Automatic Test Pattern Generation (ATPG) tools are commonly adopted solutions to provide the desired test patterns. However, those generated test patterns can also trigger non-critical (benign) faults that cause false alarms, resulting in yield loss. In this paper, we analyze the ability to detect faults based on their functional criticality given the scan architecture that enables cost-effective manufacturing testing of systolic array-based AI accelerators. We consider different approaches that classify the faults of the AI chip as critical or benign. We propose and analyze two detection schemes, which minimize the probability of false alarms. Our results show that our approaches can enable early identification of benign faults that fail the test, and thus, reduce yield loss with minimum diagnosis efforts.