CMOS four-quadrant current multiplier using switched current techniques

被引：0

作者：

Akl, Y ^{[1
]}

El-Sayed, M ^{[1
]}

Aboul-Seoud, AK ^{[1
]}

机构：

[1] Univ Alexandria, Dept Elect Engn, Alexandria, Egypt

来源：

ELECTRONICS LETTERS | 2004年 / 40卷 / 06期

关键词：

D O I：

10.1049/el:20040250

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new CMOS four-quadrant switched Current multiplier, operating from a single 3V power supply and employing two-phase clocking scheme, is proposed. The circuit is designed to perform one multiplication per clock cycle. SPICE simulations using 0.5 mum CMOS process parameters have been carried out to verify the multiplier performance.

引用

页码：359 / 360

页数：2

共 4 条

[1] S2I - A SWITCHED-CURRENT TECHNIQUE FOR HIGH-PERFORMANCE [J].