Ge oxide scavenging and gate stack nitridation for strained Si0.7Ge0.3 pFinFETs enabling 35% higher mobility than Si

We demonstrate multiple ways to reduce the D-IT of Si-cap-free low-Ge-content (25-30%) SiGe gate stack. The D-IT is reduced by i) Ge oxide scavenging via Ge condensation or by the work function metal (WFM), ii) nitridation of gate dielectrics and iii) optimized high-pressure anneal (HPA). A moderate nitridation of the interface layer (IL) is beneficial in EOT and D-IT reduction, while nitridation of the HfO2 dramatically reduces D-IT by negating an ALD TiN-induced D-IT increase. The optimized gate stack is evaluated in 8-nm-wide strained Si0.7Ge0.3 pFinFETs integrated on 300 mm Si wafers, for which a 35% improvement in high-field mobility is demonstrated as compared to Si pFinFET counterparts.