Three P-Silicon Layers in Reliable Lateral Double Diffused Metal Oxide Semiconductor Transistor

Inserting three p-layers in the drift region and buried oxide of the Lateral Double Diffused MOSFET (LDMOS) is the main goal of this paper. One of these layers is considered in the drift region and two others are in the buried oxide. Moreover, these layers have different lengths. The new structure helps to have high breakdown voltage and low on-resistance that improves Figure Of Merit (FOM) in this power transistor. Also, replacing p-silicon layer instead of silicon dioxide under the drift region reduces lattice temperature and helps to have a reliable device. The electrical parameters of the novel structure are compared with the conventional one using ATLAS simulator.