A tool to support Bluespec System Verilog coding based on UML diagrams

被引：0

作者：

Durand, Sergio H. M. ^{[1
]}

Bonato, Vanderlei ^{[1
]}

机构：

[1] Univ Sao Paulo, Inst Math & Comp Sci, BR-13566590 Sao Carlos, SP, Brazil

来源：

38TH ANNUAL CONFERENCE ON IEEE INDUSTRIAL ELECTRONICS SOCIETY (IECON 2012) | 2012年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The use of high level languages to support the development of embedded systems is a current trend. Such approach tends to reduce the development time and cost. The process of translating a high level representation to the final hardware and software architecture is desirable to be automatic encompassing as much as possible the requirements specified in high level model. This work proposes a new tool to support Bluespec System Verilog code generation based on models represented via Activity and State UML diagrams. The tool accepts as input the XMI format and the generation process is based on templates where the target language is represented.

引用

页码：4670 / 4675

页数：6

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