Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High-k Spacer for Low Power Applications

被引：52
作者：
Koley, Kalyan [1 ]
Dutta, Arka [1 ]
Syamal, Binit [2 ]
Saha, Samar K. [3 ]
Sarkar, Chandan Kumar [1 ]
机构：
[1] Jadavpur Univ, Nano Device Simulat Lab, Dept Elect & Telecommun Engn, Kolkata 700032, India
[2] Jadavpur Univ, Kolkata 700032, India
[3] SuVolta Inc, Los Gatos, CA 95032 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2013年 / 60卷 / 01期
关键词：
Fringing capacitance; gate-to-source/drain resistances; spacer; subthreshold analog; symmetric underlap DG FET; FRINGE CAPACITANCE; CMOS DEVICES; GATE; FINFETS; OPTIMIZATION; CIRCUITS; DESIGN; DGMOS;
D O I：
10.1109/TED.2012.2226724
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k. Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high-k spacers compared to its low-k counterpart.
引用
收藏
页码：63 / 69
页数：7
相关论文
共 29 条
  • [1] [Anonymous], 2008, INT TECHN ROADM SEM
  • [2] [Anonymous], 2009, SENT TCAD MAN
  • [3] [Anonymous], 2002, P INT C ION IMPL TEC
  • [4] Modeling and optimization of fringe capacitance of nanoscale DGMOS devices
    Bansal, A
    Paul, BC
    Roy, K
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2005, 52 (02) : 256 - 262
  • [5] Impact of gate underlap on gate capacitance and gate tunneling current in 16nm DGMOS devices
    Bansal, A
    Paul, BC
    Roy, K
    [J]. 2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, : 94 - 95
  • [6] Analytical subthreshold potential distribution model for gate underlap double-gate MOS transistors
    Bansal, Aditya
    Roy, Kaushik
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) : 1793 - 1798
  • [7] Impact of halo doping on the subthreshold performance of deep-submicrometer CMOS devices and circuits for ultralow power analog/mixed-signal applications
    Chakraborty, Saurav
    Mallik, Abhijit
    Sarkar, Chandan Kumar
    Rao, V. Ramgopal
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (02) : 241 - 248
  • [8] Choi YK, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P259, DOI 10.1109/IEDM.2002.1175827
  • [9] Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs
    Esseni, D
    Mastrapasqua, M
    Celler, GK
    Baumann, FH
    Fiegna, C
    Selmi, L
    Sangiorgi, E
    [J]. INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 671 - 674
  • [10] Fossum JG, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P679
123