An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

被引：45

作者：

Miyashita, Daisuke ^{[1
]}

Yamaki, Ryo ^{[2
]}

Hashiyoshi, Kazunori ^{[3
]}

Kobayashi, Hiroyuki ^{[1
]}

Kousai, Shouhei ^{[1
]}

Oowaki, Yukihito ^{[1
]}

Unekawa, Yasuo ^{[1
]}

机构：

[1] Toshiba Co Ltd, Kawasaki, Kanagawa 2128520, Japan

[2] Toshiba Co Ltd, Yokohama, Kanagawa 2478585, Japan

[3] Toshiba Microelect Corp, Kawasaki, Kanagawa 2128520, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 01期

关键词：

Analog computation; low-density parity-check (LDPC) code; LDPC decoder; multiple-valued logic (MVL); time-to-digital converter (TDC); low power; SUM ITERATIVE DECODER;

D O I：

10.1109/JSSC.2013.2284363

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm(2).

引用

页码：73 / 83

页数：11

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