A polynomial division pipelined architecture for CRC error detecting codes.

Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundacy Checking), However, the evolution towards increasing data rates increases the need for more and more sofisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbits/s to 4 Gbits/s on FPGA implementions, according to the parallelisation level (8 to 32 bits).