Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver

This work aims for providing low power, high performance receiver architecture for MC-CDMA receiver. We provide a dynamically reconfigurable FFT architecture to switchover from 64 points to 16 points based on the channel parameters(i.e.) delay spread, which otherwise would have been designed for the worst case FFT length which are our potential source of power reduction. Clock gating with FFT point reconfigurability technique is used to switchover from low length to high length FFT or vice versa. This work explores different possible ways of power reduction in the major internal blocks of FFT based on the data dependency. The simulation results are compared in terms of power dissipation, area and performance with the existing system. Results show that we could achieve a overall power reduction of more than 50% and improvement in the performance to about 24% with slight increase in area of 4.13%. The proposed architecture is modeled using Verilog HDL, simulated using NCLaunch of Cadence and synthesized with TSMC 180 nm and also with 45 nm Technology.