Benzocyclobutene polymer filling of high aspect-ratio annular trenches for fabrication of Through-Silicon-Vias (TSVs)

被引：33
作者：
Chen, Qianwen [1 ]
Huang, Cui [1 ]
Wang, Zheyao [1 ]
机构：
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
MICROELECTRONICS RELIABILITY | 2012年 / 52卷 / 11期
基金：
中国博士后科学基金;
关键词：
3-D;
D O I：
10.1016/j.microrel.2012.06.001
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Through-Silicon-Vias (TSVs) with polymer liners have potential improved electrical and mechanical reliability for three-dimensional (3D) packaging/integration applications. To address the challenge in fabrication of polymer liners in high aspect-ratio TSVs, we have developed a vacuum-assisted spin-coating technology for filling benzocyclobutene (BCB) polymer in high aspect-ratio annular trenches. The newly developed spin-coating technology employs spin-coating twice and vacuum treatment after each coating. The vacuum treatment removes the bubbles at the trench bottom trapped during spin-coating and curing, and facilities the formation of void-free BCB filling. The influences of the BCB viscosities and the spincoating parameters on the filling ability are evaluated, and upon optimization annular trenches with aspect-ratio as high as 22 have been successfully filled with no void formation, thin overburden, and slight dishing. This method is also applicable to trench filling using polymers with similar properties. (C) 2012 Elsevier Ltd. All rights reserved.
引用
收藏
页码：2670 / 2676
页数：7
相关论文
共 28 条
  • [1] [Anonymous], P IEEE INT INT TECHN
  • [2] Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement
    Bea, Jichel
    Lee, Kangwook
    Fukushima, Takafumi
    Tanaka, Tetsu
    Koyanagi, Mitsumasa
    [J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (07) : 940 - 942
  • [3] A wafer-scale 3-D circuit integration technology
    Burns, James A.
    Aull, Brian F.
    Chen, Chenson K.
    Chen, Chang-Lee
    Keast, Craig L.
    Knecht, Jeffrey M.
    Suntharalingam, Vyshnavi
    Warner, Keith
    Wyatt, Peter W.
    Yost, Donna-Ruth W.
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (10) : 2507 - 2516
  • [4] Polymer filling of medium density Through Silicon Via for 3D-Packaging
    Chausse, P.
    Bouchoucha, M.
    Henry, D.
    Sillon, N.
    Chapelon, L. L.
    [J]. 2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 790 - +
  • [5] Thick benzocyclobutene etching using high density SF6/O2 plasmas
    Chen, Qianwen
    Zhang, Dingyou
    Tan, Zhimin
    Wang, Zheyao
    Liu, Litian
    Lu, Jian-Qiang
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2011, 29 (01):
  • [6] Cu pumping in TSVs: Effect of pre-CMP thermal budget
    De Wolf, I.
    Croes, K.
    Pedreira, O. Varela
    Labie, R.
    Redolfi, A.
    Van De Peer, M.
    Vanstreels, K.
    Okoro, C.
    Vandevelde, B.
    Beynea, E.
    [J]. MICROELECTRONICS RELIABILITY, 2011, 51 (9-11) : 1856 - 1859
  • [7] Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications
    Duval, Fabrice F. C.
    Okoro, Chukwudi
    Civale, Yann
    Soussan, Philippe
    Beyne, Eric
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (06): : 825 - 832
  • [8] Hsin YC, 2011, ELEC COMP C, P1130, DOI 10.1109/ECTC.2011.5898652
  • [9] Three-dimensional silicon integration
    Knickerbocker, J. U.
    Andry, P. S.
    Dang, B.
    Horton, R. R.
    Interrante, M. J.
    Patel, C. S.
    Polastre, R. J.
    Sakuma, K.
    Sirdeshmukh, R.
    Sprogis, E. J.
    Sri-Jayantha, S. M.
    Stephens, A. M.
    Topol, A. W.
    Tsang, C. K.
    Webb, B. C.
    Wright, S. L.
    [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2008, 52 (06) : 553 - 569
  • [10] Wafer-level bonding/stacking technology for 3D integration
    Ko, Cheng-Ta
    Chen, Kuan-Neng
    [J]. MICROELECTRONICS RELIABILITY, 2010, 50 (04) : 481 - 488
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