Low Power Efficient Built in Self Test

被引：0

作者：

Muthammal, R. ^{[1
]}

Joseph, K. O. ^{[1
]}

机构：

[1] GKM Coll Engn & Technol, Chennai, Tamil Nadu, India

来源：

2011 IEEE INTERNATIONAL CONFERENCE ON MICROWAVES, COMMUNICATIONS, ANTENNAS AND ELECTRONIC SYSTEMS (COMCAS 2011) | 2011年

关键词：

Built-In-Self Test (BIST); LFSR; Transitions; Multiple Input Signature Register (MISR); Power dissipation; Automated Test Equipment (ATE);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a low power efficient Built in Self Test (BIST) with Test Pattern Generation (TPG) technique, which reduces power dissipation during testing. In general, the correlations between the consecutive test patterns are higher during normal mode than during testing mode. The proposed approach uses the concept of reducing the transitions in the test patterns generated by conventional Linear Feedback Shift Register (LFSR) RI. The transitions are reduced by increasing the correlation between the successive bits in the test pattern, which is done with the help of modified LFSR. This approach eliminates the need for an external tester. The simulation result shows that the power dissipated during testing is reduced in modified LFSR than in conventional LFSR.

引用

页数：5